 |
DRAM Products |
 |
|
|
|
|
|
|
| Memory Module for
Desktop |
|
 |
|
 |
| |
|
|
|
| The DDR2 modules are made with the newest 0.1-micron manufacturing process in Fine-Pitch Ball Grid Array (FBGA) chip packages technique, which provides some features, such as Faster data transmission, Lower power consumption, Higher capacity. |
|
| |
| |
|
 |
PC3200 / DDR400 |
|
PC3200-DDR400 DRAM Module
Overtaken by the Tornado at PC3200 MB/s
High Performance and super stability of Memory Devices PC3200 (DDR400)
will defer you from all the fear
3 times faster than the current PC133 module and 50% more in the data transfer rate compare against PC2100 DDR.
Major motherboard manufacturer in Taiwan had been working and developing closely with Memory Devices on VIA KT400, SiS 645DX and SiS 648 design. Test result shown full acceptance on this platform. In fact, with P4 1.6GHz over clocking indicated excellent performances. |
|
|
|
 |
Capacity |
|
| PC3200 / DDR400 184 Pin DDR Unbuffered DIMM |
| Capacity |
Chip Configuration |
ECC |
Chip Type |
Package |
| 128MB |
16Mx8 (x8) |
non-ECC |
DDR SDRAM |
TSOPII |
| 128MB |
16Mx16 (x4) |
non-ECC |
DDR SDRAM |
TSOPII |
| 256MB |
16Mx8 (x16) |
non-ECC |
DDR SDRAM |
TSOPII |
| 256MB |
16Mx16 (x8) |
non-ECC |
DDR SDRAM |
TSOPII |
| 256MB |
32Mx8 (x8) |
non-ECC |
DDR SDRAM |
TSOPII |
| 256MB |
32Mx8 (x9) |
ECC |
DDR SDRAM |
TSOPII |
| 512MB |
32Mx8 (x16) |
non-ECC |
DDR SDRAM |
TSOPII |
| 512MB |
32Mx8 (x18) |
ECC |
DDR SDRAM |
TSOPII |
| 1GB |
64Mx8 (x16) |
non-ECC |
DDR SDRAM |
TSOPII |
|
 |
|
|
 |
Features |
|
- Backward compatible with DDR 400/333/266 MHz motherboards
- Ensure system stability with the lowest MTFB feature
- Perform Data Transfer Rate up to 3200 MB/s
- Effectiveness overcoming PC2700 & Rambus 800
- Stability and compatibility tests guarantee to full loading operation
- Easily expand extra modules anytime
|
|
 |
|
|
 |
DRAM Settings |
|
DR400 Memory Devices/Memory Devices:
T(RAS, Active to Precharge) - 8
T(RCD, Active to CMD) - 3
T(RP, Precharge to Active) - 3
Cas Latency - 2,5
Voltage: 2,6Vdimm +/- 0,1V |
|
 |
|
|
 |
Specifications |
|
- Double Data Rate architecture
- MRS cycle with address key programs
*CAS latency: CL2, 2.5
*Burst length: 2, 4, 8
*Burst type: Sequential & Interleave
- 2 variations of refresh
*Auto refresh *Self refresh
- Serial Presence Detect support
- 2 Banks to be operated simultaneously or independently
- Package: TSOP
- 184 edge connector pads
- Clock frequency: 133/166/200MHz
- SSTL-2 interface: 2.6 Voltage +/- 0.2V
|
|

|
|
 |
Bandwidth Test |
|
| ( click to enlarge ) |
|
| * Prepared by Memory Device Lab. |
|
|
| |
|
|
|